The electronics industry is currently witnessing a major change on how data is being transferred between different parts of an electronic system. Conventional parallel input/output (typically referred to as “I/O”) schemes reach physical limitations when data rates begin to exceed just 1 Gb/s and can no longer provide a reliable, cost-effective means for keeping signals synchronized. After years of success in using parallel I/O data buses, the electronics industry is regularly replacing them with high-speed serial links. This replacement started on the system level, moving on to inter-board communications, and continuing down to chip-to-chip communications. Some current research is even focusing on how to replace parallel buses inside a single chip with such serial point-to-point schemes. This change is driven by companies across a wide-range of industries as a means to reduce system costs, simplify system design, and provide the scalability needed to meet new bandwidth requirements. Serial I/O-based designs offer many advantages over traditional parallel implementations including fewer device pins, reduced board space requirements, fewer printed circuit board (PCB) layers, easier layout of the PCB, smaller connectors, lower electromagnetic interference, and better noise immunity, as discussed in the article “High-Speed Serial I/O Made Simple”, by Abhijit Athaval and Carl Christensen, Xilinx, 2005.
Serial links can use parallel circuitry schemes and multiplexing to allow data transfer at very fast rates. (As used herein, the terms “link,” “lane” and “channel” will be used interchangeably to refer to a communication path for conveying a stream of data.) In addition, several serial links can be used in parallel to transfer large amounts of data. While each serial link typically will be completely asynchronous with respect to other serial links, digital techniques such as “channel bonding” allow combining these links and making them appear as if data is transmitted over a single channel.
Conventional integrated circuit scan test techniques rely on a large bandwidth between the device-under-test (DUT) and the automatic test equipment (ATE) performing the test. Test data from the automatic test equipment is applied to the device-under-test through scan chains, followed by some capture cycles during which the circuit response is captured in the cells of the scan chains. The circuit response is then unloaded from the circuit through the scan chains. The response is compared in the automatic test equipment to determine if the device-under-test is free of manufacturing defects. Under such circumstances, both the test stimuli and the test responses corresponding to the entire image of the scan chains are stored in the automatic test equipment memory. As bandwidth has become scarcer, the scan chains have become fewer and longer, thereby resulting in a significant increase in the overall test application time.
In current designs, as the pin-to-gate ratio continue to decrease, the number of functional pins that are accessible at the top level is decreasing as well. As high-speed I/Os are becoming prevalent, the number of digital pins that can be reused for manufacturing test is diminishing. It is becoming a luxury to have a few digital pins, if at all, for manufacturing test. On the other hand, as the semiconductor industry moves towards smaller technology nodes, new defect mechanisms are arising, thereby leading to the adoption of new fault models that require even larger numbers of test stimuli patterns targeted to identify them. Together with larger design sizes and new fault models, there is a tremendous growth in the number of test stimuli patterns that need to be applied during manufacturing test. Even if scan volume is not a concern (assuming very large automatic test equipment memory), the amount of test time needed to apply all of the different test stimuli patterns through a few long scan chains is prohibitive in practice. The circuit can be designed the in a way to support a high speed at which test stimuli patterns can be shifted into scan chains, but power dissipation during shift, and automatic test equipment limitations with regard to accuracy and precision, prohibit shifting scan data beyond a certain speed.
To mitigate the rising test cost associated with both increased test data volume (due to explosion in the number of test patterns) and test time discussed above, test compression techniques such as embedded deterministic test (EDT) have been introduced. (See, e.g., “Embedded Deterministic Test”, by J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 23, No. 5, May 2004, pp. 776-792, which article is incorporated entirely herein by reference.) A typical test compression scheme, such as embedded deterministic test, is illustrated in FIG. 1. Instead of storing the entire image of scan chains in the automatic test equipment memory, the test data is compressed and only the compressed stimuli as well as responses are stored in the automatic test equipment memory.
To facilitate such a compression scheme, a decompressor and a compactor are added on-chip. The decompressor take the compressed data at the input side and decompresses it into the data required in the scan chains for targeting specific faults. Similarly, at the output side, the responses are compressed by the compactor in such a way that there is little or no loss in the information pertaining to defect coverage of the device. Scan testing employing compression techniques like embedded deterministic test not only reduces test cost, but also helps in minimizing the volume of data transferred between the device-under-test and the automatic test equipment. The device-under-test can literally have thousands of scan chains internally between the decompressor and the compactor, but only a limited number of channels are exposed to the automatic test equipment.
For design with very few available pins for digital test, a scheme like embedded deterministic test helps as it minimizes the number of pins required for test. It should be noted, however, that even with embedded deterministic test, there is a minimum requirement for a certain number of digital pins (typically three) for the device to be tested. In order to keep the test time under control, one solution is to increase the number of internal scan chains into tens of thousands, but then routing and power constraints dictate the need for multiple decompressor and compactors distributed throughout the chip, instead of a single centrally located decompressor and compactor. Each one of these decompressors needs a channel input and each one of the compactors needs a channel output, thereby increasing the bandwidth needed for transferring data between the automatic test equipment and the device-under-test.